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  sy58611u 3.2gbps precision, lvds 2:1 mux with internal termination and fail safe input precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com march 2007 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 general description the sy58611u is a 2.5v, high-speed, fully differential lvds 2:1 mux capable of processing clocks up to 2.5ghz and data up to 3.2gbps. sy58611u is optimized to provide a buffered output of the selected input with less than 20ps of skew and less than 10ps pp total jitter. patented mux isolation design reduces crosstalk and provides superior signal integrity. the differential inputs include micrels unique, 3-pin input termination architecture that interfaces to lvpecl, lvds or cml differential signals, (ac- or dc-coupled) as small as 100mv pk (200mv pp ) without any level- shifting or termination resistor networks in the signal path. for ac-coupled input interface applications, an integrated reference voltage (v ref-ac ) is provided to bias the v t pin. the output is lvds compatible, with rise/fall times guaranteed to be less than 120ps. the sy58611u operates from a 2.5v 5% supply and is guaranteed over the full industrial temperature range (C40c to +85c). for applications that require cml or lvpecl output, consider the sy58609u and sy58610u, 2:1 mux with 400mv and 800mv output swings respectively. the sy58611u is part of micrels high-speed, precision edge ? product line. datasheets and support documentation can be found on micrels web site at: www.micrel.com . functional block diagram precision edge ? features selects between two sources and provides buffered copy of the selected input signal fail safe input C prevents output from oscillating when input is invalid or removed guaranteed ac performance over temperature and voltage: C dc-to > 3.2gbps throughput C <420ps typical propagation delay (in-to-q) C <120ps rise/fall times unique, patented internal termination and vt pin accepts dc- and ac-coupled inputs (cml, pecl,lvds) unique, patented mux input isolation design minimizes adjacent channel crosstalk ultra-low jitter design C <1ps rms cycle-to-cycle jitter C <10ps pp total jitter C <1ps rms random jitter C <10ps pp deterministic jitter 2.5v 5% power supply operation industrial temperature range: C40c to +85c available in 16-pin (3mm x 3mm) qfn package applications all sonet clock distribution fibre channel clock and data distribution gigabit ethernet clock or data distribution backplane distribution markets datacom and telecom storage ate test and measurement downloaded from: http:///
micrel, inc. sy58611u march 2007 2 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish SY58611UMG qfn-16 industrial 611u with pb-free bar-line indicator nipdau pb-free SY58611UMGtr (2) qfn-16 industrial 611u with pb-free bar-line indicator nipdau pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 16-pin qfn truth table sel output 0 in0 selected 1 in1 selected pin description pin number pin name pin function 1, 4 vt0, vt1 input termination center-tap: each side of the differential input pair terminates to the vt pin.this pin provides a center-tap to a termination network for maximum interface flexibility. see input interface applications subsection. 2, 3 vref-ac0, vref-ac1 reference voltage: these outputs bias to v cc C1.2v. they are used for ac-coupling inputs in and /in. connect vref-ac directly to the corresponding vt pin. bypass with 0.01 f low esr capacitor to vcc. due to limited drive capability, the vref-ac pin is only intended to drive itsrespective vt pin. maximum sink/source current is 0.5ma. see input interface applications subsection. 5, 6 15, 16 in1, /in1in0, /in0 differential inputs: these input pairs are the differential signal inputs to the device. inputsaccept ac- or dc-coupled differential signals as small as 100mv (200mv pp ). each pin of the pairs internally terminates with 50 ? to the v t pin. if the input swing falls below a certain threshold (typical 30mv), the fail safe input (fsi) feature will guarantee a stable output bylatching the output to its last valid state. see input interface applications subsection. 7 sel single-ended input: this single-ended ttl/cmos-compatible input selects the inputs to themultiplexer. note that this input is internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. the input-switching threshold is v cc /2. 8, 13 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors as close to the v cc pins as possible. 9, 12 /q, q lvds differential output pair: differential buffered output copy of the selected input signal. theoutput swing is typically 325mv. normally terminated 100_ across the output (q and /q). see lvds output interface applications subsection. 10, 11 gnd, exposed pad ground. exposed pad must be connected to a ground plane that is the same potential as theground pin. 14 nc no connect. downloaded from: http:///
micrel, inc. sy58611u march 2007 3 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) ................................. C0.5v to +4.0v input voltage (v in ) ......................................... C0.5v to v cc lvds output current (i out ) ................................... 10ma input current source or sink current on (in, /in)................. 50ma current (v ref ) source or sink current on v ref-ac (4) ............... 0.5ma maximum operating junction temperature ............125c lead temperature (soldering, 20sec.) ....................260c storage temperature (t s ) ...................... C65c to +150c operating ratings (2) supply voltage (v cc ) ....................... +2.375v to +2.635v ambient temperature (t a ) ..................... C40c to +85c package thermal resistance (3) qfn still-air ( q ja ) .............................................. 60c/w junction-to-board ( y jb )........................... 33c/w dc electrical characteristics (5) t a = C40c to +85c unless otherwise stated. symbol parameter condition min typ max units v cc power supply voltage range 2.375 2.5 2.625 v i cc power supply current no load, max. v cc 40 60 ma r in input resistance(in-to-v t , /in-to-v t ) 45 50 55 ? r diff_in differential input resistance(in-to-/in) 90 100 110 ? v ih input high voltage(in, /in) 1.2 v cc v v il input low voltage(in, /in) 0.2 v ih C0.1 v v in input voltage swing(in, /in) see figure 3a, note 6 0.1 1.0 v v diff_in differential input voltage swing(|in - /in|) see figure 3b 0.2 v v in_fsi input voltage threshold thattriggers fsi 30 100 mv v ref-ac ac reference voltage i vref-ac = + 0.5ma v cc -1.3 v cc -1.0 v v t_in voltage from input to v t 1.28 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratings conditionsfor extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the pcb. y jb and q ja values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. due to the limited drive capability, use for input of the same package only. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. 6. v in (max) is specified when v t is floating. downloaded from: http:///
micrel, inc. sy58611u march 2007 4 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 lvds output dc electrical characteristics (7) v cc = +2.5v 5%, r l = 100 ? across the output pair; t a = C40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v out output voltage swing (q, /q) see figure 3a 250 325 mv v diff_out differential output voltage swing |q-/q| see figure 3b 500 650 mv v ocm output common mode voltage (q, /q) see figure 5b 1.125 1.20 1.275 v d v ocm change in common mode voltage (q, /q) see figure 5b C50 50 mv lvttl/cmos dc electrical characteristics (7) v cc = 2.5v 5%; t a = C40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a notes: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. downloaded from: http:///
micrel, inc. sy58611u march 2007 5 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (8) v cc = +2.5v 5%, r l = 100 ? across the output pair; input t r /t f < 300ps, t a = C40c to +85c, unless otherwise stated. symbol parameter condition min typ max units nrz data 3.2 gbps f max maximum frequency v out > 200mv clock 2.5 3 ghz v in : 100mv-200mv 190 330 470 ps propagation delay in-to-q v in : > 200mv 150 280 420 ps t pd sel-to-q 150 450 ps input-to-input skew note 9, 10 5 20 ps t skew part-to-part skew note 11 150 ps data random jitter note 12 1 ps rms deterministic jitter note 13 10 ps pp clock cycle-to-cycle jitter note 14 1 ps rms t jitter total jitter note 15 10 ps pp t r, t f output rise/fall times(20% to 80%) at full output swing. 40 80 120 ps duty cycle differential i/o 47 53 % notes: 8. high-frequency ac-parameters are guaranteed by design and characterization. 9. input-to-input skew is the time difference between the two inputs and one output, under identical input transitions. 10. input-to-input skew is included in in-to-q propagation delay. 11. part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at the edges at the respective inputs. 12. random jitter is measured with a k28.7 pattern, measured at f max . 13. deterministic jitter is measured at 2.5gbps with both k28.5 and 2 23 C1 prbs pattern. 14. cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t jitter _ cc = t n Ct n+1 , where t is the time between rising edges of the output signal. 15. total jitter definition: with an ideal clock input frequency of f max (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. downloaded from: http:///
micrel, inc. sy58611u march 2007 6 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 functional descriptionfail-safe input (fsi) the input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the output when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mv pk (200mv pp ), typically 30mv pk . refer to figure 1b.input clock failure case if the input clock fails to a floating, static, or extremely low signal swing such that the voltage swing across the input pair is significantly less than 100mv, fsi function will eliminate a metastable condition and latch the output to the last valid state. no ringing and no undetermined state will occur at the output under these conditions. the output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mv. note that the fsi function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. refer to typical operating characteristics for detailed information. timing diagrams figure 1a. propagation delay figure 1b. fail-safe feature downloaded from: http:///
micrel, inc. sy58611u march 2007 7 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 figure 1c. sel-to-q delay input stage figure 2. simplified differential input buffer single-ended and differential swings figure 3a. single-ended swing figure 3b. differential swing downloaded from: http:///
micrel, inc. sy58611u march 2007 8 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 typical characteristicsv cc = 2.5v, gnd = 0v, v in = 100mv, r l = 100 ? across the output pair, t a = 25c, unless otherwise stated. downloaded from: http:///
micrel, inc. sy58611u march 2007 9 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 functional characteristicsv cc = 2.5v, gnd = 0v, v in = 325mv, r l = 100 ? across the output pair, t a = 25c, unless otherwise stated. downloaded from: http:///
micrel, inc. sy58611u march 2007 10 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 functional characteristics (continued) v cc = 2.5v, gnd = 0v, v in = 325mv, r l = 100 ? across the output pair, t a = 25c, unless otherwise stated. downloaded from: http:///
micrel, inc. sy58611u march 2007 11 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 input interface applications figure 4a. cml interface (dc-coupled) option: may connect v t to vcc figure 4b. cml interface (ac-coupled) figure 4c. lvpecl interface (dc-coupled) figure 4d. lvpecl interface (ac-coupled) figure 4e. lvds interface downloaded from: http:///
micrel, inc. sy58611u march 2007 12 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 lvds output interface applications lvds specifies a small swing of 325mv typical, on a nominal 1.2v common mode above ground. the common mode voltage has tight limits to permit large variations in the ground between and lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep emi low. figure 5a. lvds differential measurement figure 5b. lvds common mode measurement related products and support documentation part number function data sheet link sy58609u 4.25gbps precision, cml 2:1 mux withinternal termination and fail safe input http://www.micrel.com/_pdf/hbw/sy58609u.pdf sy58610u 3.2gbps precision, lvpecl 2:1 mux withinternal termination and fail safe input http://www.micrel.com/_pdf/hbw/sy58610u.pdf hbw solutions new products and termination applicationnotes http://www.micrel.com/page.do?page=/product-info/as/hbwsolutions.shtml downloaded from: http:///
micrel, inc. sy58611u march 2007 13 m9999-030607-a hbwhelp@micrel.com or (408) 955-1690 package information 16-pin (3mm x 3mm) qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2007 micrel, incorporated. downloaded from: http:///


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